Class Information

• Instructors:
  • Chris Vincent J. Densing
  • Adelson Chua
• Lecture: FDE Friday 10am-12nn DEEE LC1
• Lab:
  • FDET: T 8:30-11:30am
  • FDEH: Th 8:30-11:30am

Announcements

• Final grades here
• Tentative class standing as of Oct 17, 2013 here. I have given all of you perfect scores in the attendance and quizzes part. I am also waiving the must pass both requirement. Therefore, those who have failing grades in the lecture still have a chance to pass provided that their respective lab grades are high enough to pull the final grade.
• Class standing as of Oct 14, 2013 here. The last column is the third exam score needed (I haven’t checked the 3rd exam yet) to pass the course assuming the attendance and quiz grades are perfect. If you have any corrections and clarifications regarding the results, please feel free to contact me.

Lecture Slides

• Lecture 00: Introduction
• Lecture 01: HDL Overview
• Lecture 02: Simulation
• Lecture 03: Verilog
• Lecture 04: Structured Design
• Lecture 05: Programmable Devices
• Lecture 06: Issues in Digital Design
• Lecture 07: RTL and ASM
• Lecture 08: Control Logic Design
• Lecture 09: State Identification
• Lecture 10: State Identification 2
• Lecture 11: Testing and Reliability
• Lecture 12: Simulation and Faults in Sequential Circuits
• Lecture 13: DFT and BIST

Sample Exam

• First Exam