CoE 113: Advanced Computer Organization (2nd sem AY 2015-16)

Class Information

  • Instructor: Chris Vincent J. Densing
  • Lecture
    • Tues and Thurs 8:30-10am
    • EEEI room VLC
  • Laboratory
    • Tues or Thurs 2:30-5:30pm
    • EEEI room 428

Announcements

  • 6/7: Tentative grades may be viewed here. I have waived the pass lab requrement. However, people who got passing final grades but have failing lab grades (<30) will be given an INC. Requirement for completion will be a fully working lab 4 and lab 5. People who have non-INC, passing grades have until 9PM tonight to e-mail me for questions/clarifications. Afterwards, I shall upload their grades in CRS. Exam results may be claimed at room 409.
  • 5/30: Lab 5 deadline extended to June 3, 2016. EPIL will be open daily until then, from 9AM to 4PM. Just approach Bryan Ayson, Rico Maestro, or Chito Santos if the room is closed. The checker for lab 4 is also posted below to help you in implementing lab 5.
  • 5/20: Midterm exam questionnaire here
  • 5/19: Clarifications on lab 5 have been posted.
  • 5/19: Final exam on Saturday, May 21, 2016, 10AM-1PM. Room will be SC2 and SC3. Please bring A4 paper for you answer sheets.
  • 5/13: Midterm exam results can be viewed here
  • 5/4: Tentative final exam schedule is on Saturday, May 21, 2016, 10AM-1PM.
  • 4/11: Lab exercise 4 specs are now posted. This lab exercise will have double the weight (in terms of grading) compared to each of the previous lab exercises.
  • 4/5: No Lab class for the week.
  • 3/31: Midterm exam will be on Tuesday, April 5, 2016, during class hours. Please bring A4 sheets of paper for your answer sheets.
  • 3/10: Lab exercise 2 scores can be viewed here.
  • 3/8: Lab exercise 3 deadline has been extended by a week. Some addendum and errata are posted below.
  • 2/28: Please come to class on Tuesday, March 1, 2016. There will be a short quiz. Please bring yellow pad paper for answer sheets.
  • 2/23: No lab class this week (due to the holiday on Thursday). Please review the MIPS single cycle datapath from EEE 105. You can read about it in chapter 5 of Hennessy and Patterson’s Computer Organization and Design: the Hardware/Software Interface. Our next lab exercise will be based on this topic.
  • 2/11: Some updates on the naming convention for the modules of Lab exercise 2 have been posted below.
  • 2/9: Lab exercise 2 is now posted below. Just e-mail me if you have any questions.
  • 2/1: No Lab class for the week
  • 1/21: HW 1 – Prove Amdahl’s law (Lec 2, slide 9) and answer the problem on Lec 2, slide 12. Place your solutions and answers on half a sheet of pad paper and submit it next meeting.
  • 1/19: Welcome to CoE 113!

Lecture Slides

Lab Materials

  • Lab Exercise 1: Tool review
    • For setting-up the tool environment variables, use this script.
    • For the libraries, use the following files:
    • Create a module that accepts a serial input and outputs a ‘1’ (for a clock cycle) whenever the pattern “00100111” is encountered. Use the following timing constraints.
    • Deliverable/s:
      • Test waveform showing the module correctly functioning
    • Note: In case you have forgotten how to use the tool, you may refer to the CoE  111 web page last semester. The guides should still be up.
  • Lab Exercise 2: Register file and ALU
    • Required module name for register file: regfile
    • Required module name for ALU: alu
    • Checker here
    • ALU sample here
  • Lab Exercise 3: Single-cycle MIPS
    • Addendum: The following instructions should also be implemented
      • BNE
        • Format: {6’b000101, rs[4:0], rt[4:0], immed[15:0]}
        • Functionality: Essentially the same as BEQ, except that the branch is taken when the contents of rs and rt are NOT EQUAL
      • SUB
        • Format: {6’b000000, rs[4:0], rt[4:0], rd[4:0], 5’bXXXXX, 6’b100010}
        • Functionality: R-type arithmetic instruction, subtracts contents of rt from contents of rs and stores it to register specified by rd ([rs] – [rt] = [rd]).
      • SLT
        • Format: {6’b000000, rs[4:0], rt[4:0], rd[4:0], 5’bXXXXX, 6’b101010}
        • Functionality: If contents of rs is less than rt, set contents of rd to 32’d1. Otherwise, set contents of rd to 0.
    • Errata: Scoring will be as follows
      • Behavioral Model (50%)
        • 25% LW, SW
        • 15% ADD, SUB, SLT (Requires LW, SW)
        • 10% BEQ, BNE (Requires LW, SW)
      • Synthesized Model (50%)
        • 25% LW, SW
        • 15% ADD, SUB, SLT (Requires LW, SW)
        • 10% BEQ, BNE (Requires LW, SW)
    • Memory Models:
    • Checker for Tuesday class
    • Checker for Thursday class
  • Lab Exercise 4: Pipelined MIPS
    • In-class checking: testbench requirements (not necessarily in-order):
      1. Load to a register
      2. Write to memory
      3. Add two different values
      4. BEQ taken
    • In-class checking: please have the following signals ready during checking:
      • Register file contents (use $vcdplusmemon if needed)
      • Register file read ports
      • Register file write ports
      • Branch taken signal (if applicable)
      • Debug PC values for each pipeline stage
      • All other processor ports
    • Checker here. Assembly code of test program can be found in the asm directory. Scripts for running the checker can be found in the scripts directory. A reference mapped design is also provided in the mapped directory.
  • Lab Exercise 5: Pipelined MIPS II
    • Clarifications:
      • J and JAL instructions can modify the PC as early as the 2nd stage. If you indeed choose to modify it on the second stage, this should result in the flushing of 1 instruction after the J/JAL.
      • JAL instruction should update register 31 in the register file during its WB (5th) stage. This prevents any structural hazards on the register file from happening.