EEE 5 2nd Sem AY 2015-16

Class Information

  • Course Title: Introduction to Semiconductor Devices and Circuit Theory
    • 3 units lec
    • Prerequisites: Math 54, Physics 72
  • Schedule: Wed/Fri 1:00pm-2:30pm, EEEI LC1
  • Instructor: Christopher “Chito” Santos
    • email: csantos@eee.upd.edu.ph
    • consultation hours (EEEI, Rm401):
      • Wed/Fri 3:00pm-5:00pm
      • Thu 1:00pm-4:00pm
      • Fri 9:00am-12:00nn

Announcements

  • 1/20: Welcome to EEE 5! 😀
  • 1/22: Please answer the Student Directory Survey.
  • 1/30: Starting Feb03, students who still do not answer the student directory survey will be considered absent until they answer the survey.
  • 2/5: Deadline for Problem Set 1 is on February 17, 2016 (12:00pm).
  • 2/5: First long exam will be on February 19, 2016 during class hours. Please come early as much as possible.
  • 2/6: (Corrections) The deadline for Problem Set 1 is on February 10, 2016 (12:00nn) while the first long exam will be on February 12, 2016 during class hours. I apologize for the mistake.
  • 3/14: Sorry for the delay. Problem Set 2 is now available. Deadline is on March 29, 2016 (12:00pm).
  • 3/17: There will be no lecture class tomorrow 😀 It may be a good idea to use the supposed lecture time tomorrow for consultation in case you are having difficulty in any of the topics.
  • 4/20: Online class standing is now available!
  • 4/27: Problem Set 3 is now available. Deadline is on May 6, 2016 (5:00pm). Please submit on the dropbox for EEE5 in Rm 220 of EEEI.
  • 5/6: Problem Set 3 Solution is now available. Please email me asap of any correction so that I can inform the others and update the file. Please review the solution for our discussion this coming Wednesday (May 11).
  • Pre-final grades can be found here. Please take note that the comprehensive exam is not required but if taken, will be used to replace your lowest long exam. However, I have decided that if your score on the comprehensive exam is even lower, then your scores on the first three long exams will be the ones recorded. The comprehensive exam is on Tuesday, May 24 (4-7pm). Venue is at EEEI PLDT Multimedia Lecture Hall or commonly called VLC (very large classroom). The exam will still be worth 50 points although it is scheduled for 3 hours.

Course Materials

  • Class Syllabus (slides)
  • Exam 2 Coverage
    • 01 – Basic Concepts (slides)
    • 02 – KCL/KVL and Single Loop/Node Circuits (slides)
    • 03 – Mesh and Nodal Analysis (slides) (solutions)
    • 04 – Superposition, Thevenin, and Norton Theorems (slides)
  • Exam 2 Coverage
    • 05 – Semiconductors (slides)
    • 06 – Diodes (slides)
    • 07 – Diode Circuits (slides)
    • 08 – Bipolar Junction Transistors (slides)
    • 09 – Operational Amplifiers (slides)
    • 10 – Transducers and SCRs (slides)
  • Exam 3 Coverage
    • 11 – Junction Field Effect Transistors (slides)
    • 12 – MOS Field Effect Transistors and Digital Circuits (slides)
    • 13 – Integrated Circuit Logic Families (slides)

References

  • Boylestad and Nashelsky. “Electronic Devices and Circuit Theory”.    Prentice Hall.  New Jersey.
  • Chin and Jones. “Electronic Instruments and Measurements”. 2nd 1990. Prentice Hall College Division.
  • Coughlin and Driscoll. “Operational Amplifiers and Linear Integrated Circuits”. 4th 1991. Prentice Hall, Inc. New Jersey.
  • Johnson, Johnson and Hilburn. “Electric Circuit Analysis”. 2nd 1992. Prentice Hall. New Jersey
  • Pierret. “Semiconductor Device Fundamentals”. 1996. Addison-Wesley Publishing Company.
  • Sison. “Introduction to Semiconductor Devices and Circuits.” 2nd 2008. The University of the Philippines Press.
  • Tocci and Widmer. “Digital Systems: Principles and Applications”. 2001. Pearson Education Asia Pte. Ltd.