EEE 5 2nd Sem AY 2016-17

Class Information

  • Course Title: Introduction to Semiconductor Devices and Circuit Theory
    • 3 units lec
    • Prerequisites: Math 54, Physics 72
  • Schedule: TH/WF 11:30am-1:00pm, EEEI SC2 (Rm. 421)
  • Instructor: Christopher “Chito” Santos
    • email: christopher.santos@eee.upd.edu.ph
    • consultation: Tue/Wed/Fri 8:00am-11:30am at EEEI Rm. 401
  • FB Group: EEE5 Chito 2s1617

Announcements

  • 1/20: Welcome to EEE 5! xD
  • 1/26: Please add yourselves and your classmates on our FB group (EEE5 Chito 2s1617)
  • 1/30: Our online class records is now up! Please see link above.
  • 2/3: HW1 is now uploaded. Write your answers on yellow paper. Show your complete solution and box your final answers. Do not forget to include proper units. Deadline is on February 8 (Wednesday), 5:00 pm. Have your papers time-stamped and then put them on the submission box that I will put on EEEI Room 220. There is a time-stamp machine in Rm. 220.
  • 2/9: Problem Set 1 is now uploaded. Deadline is February 14, 10am.
  • 3/11: HW3 is now uploaded. Write your answers on yellow paper. Submit in the drop box at Room 220. Deadline is on Wednesday 5:00 pm. Please write your name, student number, and section on the upper right corner of each page.
  • 3/18: Problem Set 2 is now uploaded. Deadline is March 24, 5pm. Submit in the drop box at Room 220.
  • 3/30: Lecture 05 has been updated (slide 85, 86, 87, 89). Simply redownload the file.
  • 3/30: Problem Set 2 (solution) link now on this site. Correctionfor problem6 e.iii: The charge density plot should be flipped horizontally. The right side is the P-side and the net charge density at the right side is from the ionized acceptor atoms, which are negatively charged. The net charge density at the left is due to the ionized donor atoms which are positively charged.
  • 4/23: HW on digital circuits is on the slides of Lecture 09.
  • 4/26: Slides for Lecture 09 updated to include K-Maps for POS and CMOS Logic Gates.
  • 4/26: Problem Set 3 is now uploaded. I decided to move the deadline to May 02 Tuesday, 11:30am. This is so that we can discuss the solution on Tuesday/Wednesday and limit context switching as the next topic is a bit different.

Course Materials

  • Class Syllabus (pdf)
  • Exam 1 Materials
    • Lecture 01 (pdf) – Basic EEE Concepts
    • Lecture 02 (pdf v2) – Kirchhoff’s Laws and Single Node/Loop Circuits
    • Lecture 03 (pdf v3) – Mesh and Nodal Analyses
    • Lecture 04 (pdf) – Superposition, Source Transformation, Thevenin/Norton Theorems
    • Lecture 05 (pdf) – Semiconductor Fundamentals
    • Lecture 06 – PN Junction Diodes
    • Lecture 07 – Bipolar Junction Transistors
    • Lecture 08 (pdf v1)- Field Effect Transistors
    • Lecture 09 (pdf) – Digital Circuits

References

  • Hayt, W.H., Kemmerly, J.E. & Durbin, S.M. (2007). “Engineering Circuit Analysis”. McGraw-Hill Higher Education
  • Johnson, Johnson & Hilburn. “Electric Circuit Analysis”. 2nd 1992. Prentice Hall. New Jersey
  • Pierret. “Semiconductor Device Fundamentals”. 1996. Addison-Wesley Publishing Company.
  • Sison. “Introduction to Semiconductor Devices and Circuits.” 2nd 2008. The University of the Philippines Press.
  • Boylestad and Nashelsky. “Electronic Devices and Circuit Theory”.    Prentice Hall.  New Jersey.
  • Chin and Jones. “Electronic Instruments and Measurements”. 2nd 1990. Prentice Hall College Division.
  • Coughlin and Driscoll. “Operational Amplifiers and Linear Integrated Circuits”. 4th 1991. Prentice Hall, Inc. New Jersey.
  • Tocci and Widmer. “Digital Systems: Principles and Applications”. 2001. Pearson Education Asia Pte. Ltd.